Design and construction of multiple logic signal analyzer
Date
4-2000
Degree
Bachelor of Science in Applied Physics
College
College of Arts and Sciences (CAS)
Adviser/Committee Chair
Nelio C. Altoveros
Abstract
An instrument for detecting and storing multiple and simultaneous logic signals was designed, implemented and tested. The device used HM6264 8192 word x 8-bit static which acted as the external memory that initially store the sample data. The writing and reading of data to and from the SRAM was controlled by the state machines programmed in an EPM71288 EPLD. The device was interfaced to an 80486 microcomputer system through the computer's AT bus. A graphic design software was developed to control the instrument for data collection and storage to a file. A separate program was also developed to output the data collected in a waveform format. A 4-bit binary counter and a z-8- microprocessor were tedted using theinstrument. The gathering of data with the counter clock frequency of 1.25 MHZ, 0.625 MHZ., 0.315 MHZ and 0.15625 MHZ
Language
English
Location
UPLB Main Library Special Collections Section (USCS)
Call Number
Thesis
Recommended Citation
Visleño, Juvie J., "Design and construction of multiple logic signal analyzer" (2000). Undergraduate Theses. 10608.
https://www.ukdr.uplb.edu.ph/etd-undergrad/10608
Document Type
Thesis